A Phase-Locked Loop (PLL) circuit can be used to generate an output clock signal based on a reference clock signal. For example, FIG. 1 is a block diagram of a known PLL circuit 100. The PLL circuit 100 includes a phase detector 110 that receives a reference clock signal and a feedback clock signal. Based on a difference between these two signals (e.g., a difference in phase or frequency), the phase detector 110 provides up and down signals to a charge pump 120. A Voltage Controlled Oscillator (VCO) 140 generates an output clock signal at a frequency that is based on a signal received from the charge pump 120. That is, an up signal from the phase detector 110 will cause the VCO 140 to increase the frequency of the output clock signal (and a down signal will cause the VCO 140 to decrease the frequency). A divider 150 divides the output clock signal by N to create the feedback clock signal that is provided to the phase detector 110. A loop filter 130 between the charge pump 120 and the VCO 140 may filter a high frequency signal from the charge pump 120 to create a lower frequency signal that can be used to control the VCO 140.
The frequency of the output clock signal generated by the PLL circuit 100 will initially vary. Eventually, however, the PLL circuit 100 xe2x80x9clocksxe2x80x9d and the output clock signal remains at an appropriate frequency (e.g., based on the frequency of the reference clock signal and the value of N).
Even after the PLL circuit 100 achieves lock, the output clock signal may contain an amount of xe2x80x9cjitterxe2x80x9d (i.e., variations in the clock signal""s rising and falling edges as compared to an ideal clock signal). Note that output jitter may a limiter for embedded clock data recovery based serial links, and thus should be reduced.
In general, the amount of jitter in the output clock signal is related to the overall gain of the PLL circuit 100. In particular, a PLL circuit 100 with a higher gain will have a larger amount of jitter as compared to a PLL circuit with a lower gain in the regime where reference clock jitter is the determinant one and an internal PLL needs it small.
The gain of individual elements in the PLL circuit 100 contribute to the overall gain of the PLL circuit 100. For example, the gain of the VCO 140 will contribute to the overall gain (and jitter) of the PLL circuit 100. Thus, reducing the gain of the VCO 140 will lead to reduced jitter. However, reducing the gain of the VCO 140 will also reduce the range of frequencies at which the VCO 140 can operatexe2x80x94resulting a less versatile PLL circuit 100. Moreover, a PLL circuit 100 associated with an Input Output (IO) system may need to operate at a large range of frequencies (e.g., because of differences that may exist between the PLL circuits in a transmitting device and a receiving device).
The gain of the charge pump 120 also contributes to the overall gain (and jitter) of the PLL circuit 100. Note, however, that a charge pump 120 with a higher gain will achieve lock faster than a charge pump 120 that has a lower gain. That is, reducing the gain associated with the charge pump 120 will cause the PLL circuit 100 to achieve lock more slowly (or even prevent lock from being achieved at all).